Multi-computer communications systems commonly employ packet switching techniques for handling high-volume data in a computer network by breaking apart data messages into fixed length packets that are transmitted to a destination, commonly a memory location, through the most expedient route. Switching techniques, and switches thereof, are especially useful for interconnecting processors in multiprocessor computers and should be applicable to recent transmission standards, such as scalable coherent interface (SCI). The switching of fixed length packets are commonly performed in accordance with International Communication Standards, such as the broadband integrated services digital network (BISDN) for transmitting voice, video and data over a data communication line. A data packet switching unit that arranges output data so as to be staggered in time is described in European Patent 547836, herein incorporated by reference. It is desired that data packet switching be provided without having to rely on arranging data so as to be staggered in time and yet still providing synchronization between the multiple computers comprising the communication system.
In a multi-processor communication system, it is important to have a rapidly reconfigurable interconnecting switch so that any one processor may communication with any other processor within the shortest possible latency, that is, within the shortest possible time between initiating a request for data and the beginning of the actual data transfer. In the multi-processor communication system, simultaneous processing may be performed with two or more processors processing together and any unnecessary latency would degrade the corresponding results.
Conventional digital switches, such as a banyan switch known in the art, require many clock cycles to set up an interconnection during a reconfiguration operation of the multi-processors of the communication system, thus, limiting the minimum time of the latency parameter, thus, limiting the latency to at least many clock cycles. It is desired that the reconfigurability of the multi-processor computer system be accomplished in the shortest possible time and not be restricted to multiple clock cycles.
It is a primary object of the present invention to provide a network interconnecting switch for rapidly interconnecting processors in a multi-processor communication system within a maximum time of a few clock cycles and a minimum time of less than one clock cycle and yet provide synchronization between the processors.
It is another object of the present invention to provide a network interconnecting switch that provides contention resolution means between one or more processors that are competing for the same resource, such as the same location in a memory within one of the processors.
It is a further object of the present invention to provide for a network interconnecting switch utilizing optical and optoelectronic devices brought together by optical fibers serving as waveguide elements.